108位前导0计数器的电路设计与优化

Design and Optimization of the 108-bit Leading Zero Counter's Circuit

采用2位分组进行并行分工计数,使用二叉树的电路结构进行108位前导0计数器电路设计.采用2位分组的108位前导0计数器电路进行PT分析的时序为0.17,而采用8位分组的RTL级代码进行DC综合的时序为0.21,通过比较发现设计电路在速度上比RTL级代码快了19%.

This paper adopts 2-bit parallel packet to count respectively,108 leading zero counter circuit design uses the structure which is two binary tree.The timing that 108-bit leading zero counter using 2-bit packet which is analyzed by PT is 0.17,and the timing that the RTL code using 8-bit packet which is analyzed by DC is 0.21,Comparative experice tell us that the design circuit is 20%faster than the RTL code in speed.