摘要
针对目前低密度奇偶校验(LDPC)码译码复杂度大、速率低、占用资源多的问题,深入研究了LDPC码的译码算法.在加性高斯白噪声(AWGN)信道下,对适合硬件实现的最小和译码算法进行了仿真,得到了最佳的量化方案和译码迭代次数.在两种改进的最小和译码算法的基础上,设计出一种新型的LDPC码部分并行译码器,并在Xilinx公司的FPGA XC5VLX110T上完成了算法的实现和时序的优化.经测试,该译码器的吞吐量达到152Mb/s.
Considering the code decoding complexity,low decoding rate,resource-intensive of LDPC,the decoding algorithm of LDPC codes is studied.The min-sum algorithm is simulated under Matlab,which is based on Additive White Gaussian Noise(AWGN)channel,and the best quantization scheme and the number of iterations are obtained.Then combining two improved min-sum algorithm,designs a new partly parallel LDPC code decoder is designed.The decoder has been realized on Xilinx′s FPGA XC5VLX110 T. According to timing sequence optimization,the decoder′s throughput is up to 152 Mb/s.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第6期54-57,61,共5页
Microelectronics & Computer
基金
国家自然科学基金(61201388)
