电荷泵锁相环中相位噪声的抑制和讨论

An Issue of Jitter in the Design of Charge-pump Phase Locked Loop

旨在介绍一种抑制电荷泵锁相环 ( CPPL L)中相位噪声 ( Jitter)的电路结构。文章在分析 CPPL L 对 Jitter抑制原理的基础上 ,指出 Jitter虽然无法被环路自身的跟踪作用根除 ,但却可以通过对鉴频鉴相器 ( PF D)的改进而得到较好地抑制。为了验证改进电路的效果 ,文中给出了实验数据 ,实验结果证明新的电路结构可以较好地抑制 Jitter。

An issue of Jitterchoking in the design of charge pump phase locked loops (CPPLL) is presented in this paper After describes the principle of Jitterchoking, we know Jitter can′t be eliminated by phase trace of the loop,but it can be choked mainly by improving the design of PFD An experiment is given to verify the degree of improvement, and the result proved that the improvement of PFD can choke Jitter validly