期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

模拟集成电路二维Stack生成及模块合并算法(英文)

Two-Dimensional Stack Generation and Block Merging Algorithms for Analog VLSI
下载PDF
导出
摘要 在模拟集成电路设计中,关于X轴和Y轴同时对称的Stack,以及模块之间的合并,对于增加器件之间的匹配和控制寄生是至关重要的.描述了模拟集成电路二轴对称Stack生成算法和模块合并算法.通过对于对称欧拉图和对称欧拉路径的研究,得出了多项理论结果.在此基础上,提出了时间复杂度为O(n)的伪器件插入算法、对称欧拉路径构造算法和二轴对称Stack生成算法.生成的Stack,不但关于X轴和Y轴对称,而且具有公共质心(common- centroid)的结构.还描述了模块合并算法,给出了计算最大合并距离的公式.该算法本质上是独立于任何拓扑表示的.实验结果验证了算法的有效性. In analog VLSI design, 2-dimensional symmetry stack and block merging are critical for mismatch minimization and parasitic control. Algorithms for analog VLSI 2-dimensional symmetry stack and block merging are described. Several theoretical results are obtained by studying symmetric Eulerian graph and symmetric Eulerian trail. Based on them, an O(n) algorithm for dummy transistor insertion, symmetric Eulerian trail construction and 2-dimensional symmetry stack construction is developed. The generated stacks are 2-dimensional symmetric and common-centroid. A block merging algorithm is described, which is essentially independent of the topological representation. Formula for calculating the maximum block merging distance is given. Experimental results show the effectiveness of the algorithms.
作者 刘锐 董社勤 洪先龙 龙迪 顾钧
机构地区 中国科学院软件研究所 清华大学计算机科学与技术系 清华大学计算机科学与技术系 香港科技大学计算机系
出处 《软件学报》 EI CSCD 北大核心 2004年第5期641-649,共9页 Journal of Software
基金 国家自然科学基金90307005 60121120706 国家自然基金与香港研究资助局联合资助60218004 美国国家自然科学基金CCR-0096383 国家高技术研究发展计划(863)2002AA1Z1460~~
关键词 模拟集成电路 二维Stack 模块合并 对称欧拉路径 Algorithms Graph theory Optimization Theorem proving Two dimensional
分类号 TP302 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献24

  • 1Cohn JM, Garrod DJ, Rutenbar RA, Carley LR. KOAN/ANAGRAM II: New tools for device-level analog placement and routing.IEEE Journal of Solid State Circuits, 1991,26(3):330-342.
  • 2Cohn J, Garrod D, Rutenbar R, Carley LR. Analog Device-Level Layout Generation. Norwell: Kluwer, 1994.
  • 3Garrod D, Rutenbar R, Carley LR. Automatic layout of custom analog cells in ANAGRAM In: Proc. of the ACM/IEEE Int. Conf.Computer-Aided Design (ICCAD). Nov. 1988. 544-547.
  • 4Gatti U, Maloberti F, Liberali V. Full stacked layout of analog cells. In: Proc. of the IEEE Int'l Symp. on Circuits and Systems.1989. 1123-1126.
  • 5Malavasi E, Pandini D. Optimum CMOS stack generation with analog constraints IEEE Trans. on Computer-Aided Design,1995,14:107-122.
  • 6Arsintescu GB, Spanoche SA. Global generation of MOS transistor stacks. IEEE EuroDAC, 1996.
  • 7Basaran A, Rutenbar RA. An O(n) algorithm for transistor stacking with performance constraints In: Proc. of the IEEE/ACM DAC.1996. 221-226.
  • 8Zeng X, Li MY, Zhao WQ, Tang PS, Zhou D. Parasitic and mismatch modeling for optimal stack generation. In: Proc. of the IEEE ISCAS 2000, Geneva, Switzerland, May 23-31, 2000.
  • 9Bastos J, Steyaert M, Graindourze B, Sansen W. Matching of MOS transistors with different layout styles. In: Proc. of the IEEE Int'l Conf. on Microelectronic Test Structures 1996. 17-18.
  • 10Bastos J, Steyaert M, Graindourze B, Sansen W. Influence of die bonding on MOS transistor matching. In: Proc. of the IEEE Int'l Conf. on Microelectronic Test Structures 1996. 17-31.

二级参考文献13

  • 1Otten R. Automatic floorplan design. In: Proceedings of the 19th ACM/IEEE Design Automation Confrence. 1982. 261-267.
  • 2Wong DF, Liu CL. A new algorithm for floorplan design. In: Proceedings of the 23rd ACM/IEEE Design Automation Conference.1986. 191-107.
  • 3Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. Rectangle-Packing-Based module placement In: Proceedings of the IEEE International Conference Computer-Aided Design. 1995.472-479.
  • 4Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. VLSI module placement based on rectangle-packing by the sequence paic IEEE Transactions on Computer-Aided Design, 1996,15(11):1518-1524.
  • 5Nakatake S, Fujiyoshi K, Murata H, Kajitani Y. Bounded-Slicing structure for module placement Technical Report, Institute of Electronics, Information, and Communication Engineers (IEICE),1994,VLD94(313): 19-24.
  • 6Nakatake S, Fujiyoshi K, Murata H, Kajitani Y. Module placement on BSG-structure and IC layout applications In: Proceedings of the IEEE International Conference Computer-Aided Design. 1996. 484-491.
  • 7Hong XL, Huang G, et al. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In:Proceedings of the IEEE International Conference Computer-Aided Design 2000. 2000.
  • 8Guo PN, Cheng CK, Yoshimura T. An O-tree representation of non-slicing floorplan and its applications In: Proceedings of the 36th ACM/IEEE Design Automation Conference. 1999. 268-273.
  • 9Tang XP, Wong DF. FAST-SP: A fast algorithm for block placement based on sequence pair. In: Proceedings of the ASP-DAC.2001, 521-526.
  • 10Murata H, Fujiyoshi K, Daneko M. VLSI/PCB placement with obstacles based on sequence pair. IEEE Transactions on Computer-Aided Design, 1998,17(1).

共引文献1

软件学报
2004年 第5期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部