摘要
提出了一个用于估计 RL C互连树驱动点导纳的闭端等效 π模型 ,并将其用于驱动复杂 RL C互连树的逻辑门延时的估计中 .与其他方法相比 ,它具有结构简单。
A close ended equivalent π model for RLC interconnect tree to estimate the driving point admittance is proposed.The model can be applied to delay estimation of gate driving large RLC interconnect tree.It features simple construction and high precision,hence it is superior to other methods.
基金
国防预研基金资助项目 (批准号 :413 2 3 0 2 0 2 0 4)~~
关键词
逻辑门延时
RLC互连树
驱动点导纳
delay of logic gate
RLC interconnect tree
driving point admittance