期刊文献+

驱动复杂RLC互连树的逻辑门延时 被引量:2

Delay of Logic Gate Driving Large RLC Interconnect Tree
下载PDF
导出
摘要 提出了一个用于估计 RL C互连树驱动点导纳的闭端等效 π模型 ,并将其用于驱动复杂 RL C互连树的逻辑门延时的估计中 .与其他方法相比 ,它具有结构简单。 A close ended equivalent π model for RLC interconnect tree to estimate the driving point admittance is proposed.The model can be applied to delay estimation of gate driving large RLC interconnect tree.It features simple construction and high precision,hence it is superior to other methods.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第8期1036-1040,共5页 半导体学报(英文版)
基金 国防预研基金资助项目 (批准号 :413 2 3 0 2 0 2 0 4)~~
关键词 逻辑门延时 RLC互连树 驱动点导纳 delay of logic gate RLC interconnect tree driving point admittance
  • 相关文献

参考文献8

  • 1Pillage L T,Rohrer R A. Asymptotic waveform evaluation for timing analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst,1990,9 (4):352
  • 2Feldman P,Freund R. Efficient linear circuit analysis by Pade approximation via the Lanczos process. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1995,14 (5): 639
  • 3Kashyap C V,Krauter B L. A realizable driving point model for on-chip interconnect with inductance. Proc DAC 2000:190
  • 4Qian J,Pullela S,Pillage L. Modeling the ''effective capacitance'' for the RC interconnect of CMOS gates. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1994,13 (12) : 1526
  • 5Devgan A,O'Brien P R. Realizable reduction of RC interconnect circuits. Proc ICCAD, 1999 : 204
  • 6El-Moursy M A, Friedman E G. Shielding effect of on-chip interconnect inductance. Proc ACM Symposium on Great Lakes Symposium on VLSI, 2003 : 165
  • 7Kahng A B,Muddu S. Efficient gate delay modeling for large interconnect loads. Proc IEEE Multi-Chip Module Conf,1996:202
  • 8http:∥public. itrs. net/files/2000UpdateFinal/2kUdFinal.htm

同被引文献16

  • 1Ismail Y I,Friedman E G,Neves J L.Equivalent Elmore delay for RLC trees.IEEE Trans on CAD,2000,19(1):83.
  • 2Kashyap C V,Krauter B L.A realizable driving point model for on-chip interconnect with inductance.Proc DAC,2000:190.
  • 3Qian J,Pullela S,Pillage L.Modeling the effective capacitance for the RC interconnect of CMOS gates.IEEE Trans on CAD,1994,13(12):1526.
  • 4Devgan A,O'Brien P R.Realizable reduction of RC interconnect circuits.Proc ICCAD,1999:204.
  • 5El-Moursy M A,Eby G.Friedman,Shielding effect of on-chip interconnect inductance.Proc ACM Great Lakes Symposium on VLSI,2003:165.
  • 6Yang Xiaodong,Cheng C K,Ku W H,et al.Hurwitz stable reduced order modeling for RLC interconnect trees.Proc ICCAD,2000:222.
  • 7Brocco L M,McCormick S P,Allen J.Macro-modeling CMOS circuits for timing simulation.IEEE Trans on CAD,1988,7(12):1237.
  • 8Weste N H,Eshraghian K.Principles of CMOS VLSI design.New York:Addson Wesley,1993.
  • 9Kahng A B,Muddu S.Efficient gate delay modeling for large interconnect loads.Proc IEEE Multi-Chip Module Conf,1996:202.
  • 10L T Pillage,et al.Asymptotic waveform evaluation for timing analysis[J].IEEE Trans.Computer-Aided Design,1990,9(4):352-366.

引证文献2

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部