变参数RS编码器IP核的设计与实现

The IP Core Design for Varied Parameters RS Encoder

设计了一种码长可变、纠错能力可调的 RS编码器。该 RS编码器可对常用的 RS短码进行编码 ,可做成 IP核 ,为用户提供了很大的方便 ;采用基于多项式乘法理论 GF( 2 m)上的 m位快速有限域乘法的方法 ,提高了编码电路的运算速度 ;同时给出了程序仿真结果 ,并在 Xilinx的 FPGA上进行了硬件验证。

In this paper, we design an RS encoder with a varied length of code and rectified ability. It can encode for ordinary RS short code. This paper introduces four bites rapid multiplication based on the multinomial multiplicative theory of Galois to improve the operative rate of encoding circuit. Finally, the simulation result by Verilog7.0 and verfication with FPGA of Xilinx are presented and prove the design proper.