VHDL语言设计可综合的微处理器内核

Synthetic VHDL Microprocessor Core Design

详细介绍了用VHDL语言设计可逻辑综合的教学实验用CPU的过程。CPU指令系统构架采用RISC结构 ,设计上使用结构化编程方法 ,将CPU内核按照功能划分为不同的模块 ,采用VHDL语言设计每一个模块的内部功能和外围接口。所有的功能模块组合起来后 ,通过EDA工具进行CPU内核的逻辑综合和功能仿真 。

This paper describes a synthetic RISC architecture CPU design and implementation in detail for teaching experiment.To use structure programming method,making the instruction system architecture design,then divide the microprocessor into different function units.Write VHDL code to describle internal function and external interface of each unit.CPU core was simulated and synthesized by EDA tools after combine all units.In the end,CPU core was implemented in programmable logic device.