基于ISP的信号接口设计

Design of Signal Interface Based on ISP

利用ISP器件和VHDL语言设计的专用信号接口由继电器阵列、多路开关和相关驱动电路组成。采用计算机ISA总线控制,通过继电器触点切换实现测试信号的分配。并用VHDL语言描述逻辑、定义管脚、增加读写、编译原理图、产生JED文件,将JED文件存入可编程逻辑器件以完成编程设计。

The special signal interface that was designed with ISP devices and VHDL consists of the relay-array, multi-switch circuit and correlative drive circuit. The allocation of test signals can be implemented through the switching of the contact spot controlled by ISA bus via. VHDL language is used to describe, define the base pins, add read-write and compile schematics, create the JED files, and download JED files into CPLD to complete the design.