ORC的全局指令调度技术

Global Instruction Scheduling Technique in ORC

IA 6 4是一种崭新的体系结构 ,它为挖掘程序中潜在的指令级并行提供了丰富的硬件支持 ,例如 :大寄存器组、(控制 /数据 )投机、谓词等 .Itanium是IA 6 4的一个具体实现 .该文作者将Bernstein的基于超标量处理机的全局指令调度算法应用于显式并行 (EPIC)的Itanium处理机上 .在结合Itanium处理机特性的同时 ,作者对Bernstein的算法有以下两点创新 :(1)应用层次化区域 .相对于传统的扁平区域 ,这样的区域具有很强的灵活性并提供了调度器大小合适的调度范围 ,使其既能充分利用硬件资源又能够有效地控制调度的时间和空间开销 .(2 )集成P Ready指令调度 .P Ready是在与Bernstein算法框架差异很大的上下文中提出的 .P Ready指令调度能够把优先级高的指令尽早调度即使这条指令并没有在所有经过它的执行路径上解除数据依赖 .集成P Ready指令调度到Bernstein的算法框架上是十分有意义的 .作者在“基于Itanium处理机的开放源码编译器ORC”中实现了该文介绍的算法 ,实验结果显示全局指令调度器对CPU2 0 0 0int基准测试例平均有 8.4 %的运行时加速比 .作为应用层次化区域的优越性的一个反映 ,调度指令跨越嵌套循环最高可取得 12 .9%的运行时加速比 .此外 ,P Ready指令调度对CPU2 0 0 0int的测试例平均有 1.37%的运行?

IA-64 is a novel architecture that provides ample hardware support to exploit instruction level parallelism. And it is exemplified by the Itanium processor. Authors adapt D. Bernstein's algorithm, which is targeted for superscalar processor, to EPIC processor Itanium. And authors take full advantage of Itanium specific details, and have two improvements to D. Bernstein's algorithm: (1) Apply hierarchical region structure into this algorithm. (2) Integrate P-Ready instruction scheduling. P-Ready is proposed under a context that is totally different with D. Bernstein's. The algorithm proposed is implemented in the open research compiler ORC. Authors' results show that the global scheduler achieves 8.4% runtime speedup on CPU2000int benchmarks. As an indicator of the advantage of applying hierarchical region structure, the technique that moves instruction across nested loops can obtain up to 12.9% runtime speedup. The integrated P-Ready instruction scheduling can obtain up to 7.6% speedup and 1.37% speedup on average for all CPU2000int benchmarks.