基于Verilog-A行为描述模型的PLL系统设计

System Design of PLL Based on Behavioral Model Using Verilog-A

分析了模拟硬件描述语言Verilog A的特点 ,介绍了一种基于Verilog AHDL行为模型的模拟电路自顶向下设计方法。这种方法适用于片上系统 (SOC)模拟部分的设计。根据压控振荡器 (VCO)和二阶无源低通滤波器 (LPF)的数学模型 ,建立了它们基于Verilog A的行为模型 ,并用该方法实现了包含中心频率为 12 0MHz的VCO和截止频率为 30 0 0kHz的LPF在内的电荷泵锁相环系统设计。最后利用CadenceSpectre仿真器对模型进行了验证及PLL系统级仿真。

The characteristics of Verilog-A HDL are introduced and a top-down design method of analog circuits based on Verilog-A behavioral models is proposed. By this method, a PLL contained a VCO behavioral model with center frequency 120 MHz and a two-order passive filter with cut-off frequency 300.0 kHz is implemented. The behavioral models are verified and used in PLL system simulation by the tool of Cadence Spectre.