摘要
介绍一种适于数字CMOS工艺实现的全差分运算放大器的设计。该放大器用于电源电压为3V,分辨率为10位,采样频率为40MHz的流水线结构AD的采样保持和级间增益电路中。该放大器的结构为折叠一级联结构,在0.35μmCMOS工艺中带宽为162MHz,开环增益为73dB,功耗为1.92mW。
The design of a fully differential op--amp is presented, in this paper, which is sutiable for implemen-tation in digitial CMOS technology. The amplifier is used in the samping-holding and inter-stage sub-gaincircuits of 10-bit, 40 MHz pipeline AD counter. The structure of the amplifier presented consists of a folded-cascode for 0.35μm CMOS, the gain-bandwidth is 162 Mhz, open loop gain 73db and power consumption 1.92mW.
出处
《电子与封装》
2004年第4期54-56,共3页
Electronics & Packaging
