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分数N频率综合器的杂散分析 被引量:6

Spur analysis of fractional-N frequency synthesizers
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摘要 杂散是影响分数N频率综合器性能的重要指标。针对传统无补偿频率综合器和采用ΣΔ调制技术的分数N频率综合器的杂散输出进行理论分析。在传统无补偿频率综合器的分析中引入附加相移满足锁定条件,同时采用新的分析方法使得各杂散分量更加明显。在对于ΣΔ调制技术的频率综合器,通过线性分析指明带宽选取与残留相差及高频端噪声抑制能力间的关系,并用时域模型给出环路非线性如鉴相鉴频器的死区和电荷泵充放电电流的失配使得频率综合器带内输出噪声频谱恶化30dB。 Spur is the key specification that affects the performance of fractional-N frequency synthesizers. The spur for traditional compensationless and ΣΔ modulated fractional-N frequency synthesizers was analyzed theoretically to make the spur components more explicit. An extra phase shift was introduced into traditional compensation-less fractional-N frequency synthesizers to satisfy the locked condition. For ΣΔ modulated fractional-N frequency synthe- sizers, a relationship was developed for the loop bandwidth as a function of the residual phase error and the high frequency noise rejection using linear analysis. Analysis using the time field model shows that loop nonlinearities, such as the dead-zone in phase-frequency detectors and the mismatch between the charge and discharge currents in the charge pump, can reduce the output noise by 30 dB.
出处 《清华大学学报(自然科学版)》 EI CAS CSCD 北大核心 2004年第7期958-961,共4页 Journal of Tsinghua University(Science and Technology)
关键词 分数Ⅳ频率综合器 杂散 SIGMA-DELTA调制 fractional-N frequency synthesizer spur sigma-delta modulation
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参考文献6

  • 1周裕和,苗镇南.变带宽滤波小数频率合成器[J].军事通信技术,1994,15(4):18-25. 被引量:1
  • 2郭仿军.小数分频锁相环的杂散分析[J].重庆邮电学院学报(自然科学版),2002,14(2):84-87. 被引量:10
  • 3FAN Yiping. Modeling and simulation of ΣΔ frequency synthesizers [A]. IEEE International Symposium on Industrial Electronics [C]. Pusan, South Korea: IEEE, 2001. 684-689.
  • 4Rhee W, Song B, Ali A. A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b third-order delta-sigma modulator [J]. IEEE Journal of Solid-State Circuits, 2000, (10): 1453-1460.
  • 5Miller B, Conley R J. A multiple modulator fractional divider [J]. IEEE Trans on Instrumentation and Measurement, 1991, 40(6): 578-583.
  • 6Galton I. Delta-sigma data conversion in wireless transceivers [J]. IEEE Trans on Microwave Theory and Techniques, 2002, 50(1): 302-315.

二级参考文献1

  • 1万心平.通讯工程中的锁相环路[M].西安:西北电讯工程学院,1980..

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  • 1张春荣.雷达捷变频频率综合器技术及跳频时间测量[J].火控雷达技术,2004,33(4):42-45. 被引量:8
  • 2张春荣.电子设备电磁兼容设计研究[J].火控雷达技术,2007,36(2):10-15. 被引量:3
  • 3ETSI EN 302 208 - 1 V1.3. 1, Electromagnetic compati- bility and Radio spectrum Matters (ERM);Radio fre- quency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W [ S ]. Ce- dex: ETSI,2010.
  • 4FCC code of federal regulations title 47 chapter 1 part 15, radio - frequency device [ S]. Washington : FCC, 1999.
  • 5KELIU Shu, EDGAR Sanchez -Sinencio. CMOS PLL synthesizer: analysis and design [ M ]. Boston: Springer, 2005:40 - 120.
  • 6HENG Chunhuat, SONG Bang- Sup. A 1.8 GHz CMOSfractional - N frequency synthesizer with randomized mul- tiphase VCO [ J ]. IEEE Journal of Solid - state Circuits, 2003,38(6) :848 - 858.
  • 7I-IUSSEIN A E, ELMASRY M I. A fractional -N fre- quency synthesizer for wireless communications [ C ] l/ IEEE international symposium on circuits and systems, Arizona: electrical and electronics engineers institute,2002:513 - 516.
  • 8GALTON I. Delta - sigma data conversion in wireless transceivers [ J]. IEEE transactions on microwave theory and techniques, 2002, 50(1):302-315.
  • 9Cicero S V.An adaptive PLL tuning system arhitecture Combining high spectral purity and fast settling time[J].IEEE J.Solid-State Circuits,2000,35 (4):490-502.
  • 10Cheng Kuo-Hsing and Yang Wei-Bin.A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop.IEEE CAS-Ⅱ,2003,50(11):892-896.

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