摘要
简要介绍了传统的继电保护装置数据采集的过程,通过分析FIFO(First inFirst out)和A/D的操作时序搭配,并合理设计CPLD(ComplexProgrammableLogicDevice),设计了一种A/D自动采样接口。CPU只要发出一个脉冲信号,该接口就能依次完成16路模拟通道切换、A/D转换、数据存储等控制,当一个采样周期的所有模拟通道数据转换完成后,及时向CPU发出中断请求,CPU即可从相应的FIFO读出所有通道数据。不仅减轻了CPU的任务,提高系统执行效率,还可简化软件编程,有助于改进软件的模块化设计水平。
The sampling process of traditional relays is introduced. On analyzing the timing of FIFO and A/D, a new kind of auto-sampling interface based on CPLD is well designed. Given just one pulse by CPU, the interface will finish channels-switching, A/D-converting and data-storing in the correct order automatically by itself. After finishing all channels' sampling in each sampling period, it sends an end signal to interrupt CPU, and CPU reads all the channels data from FIFO. This design can really alleviate the task of CPU, improve the operation efficiency, simplify the design of software, and conduce to the design of modularization.
出处
《继电器》
CSCD
北大核心
2004年第16期44-46,共3页
Relay