基于DDS+PLL技术的高频时钟发生器

High-frequency Clock Generator Based on DDS Hybrid PLL

针对直接数字频率合成 ( DDS)和集成锁相环 ( PL L )技术的特性 ,提出了一种新的 DDS激励 PL L系统频率合成时钟发生器方案。分析了频率合成系统相位噪声和杂散抑制的方法 ,介绍了主要器件 AD985 4和 ADF410

This paper introduces the operating theory of DDS and PLL technic, presents a new highfrequency clock generator project of DDS hybrid PLL system based on the analysis of the output development results of the phase noise and spurious suppression method,analyzes the functions of chip AD9854 and ADF4106.