基于门控时钟的低功耗MCU的设计与实现

The Design and Implementation of Low Power MCU Based on Clock-gating

文章研究了一种基于门控时钟的低功耗MCU的设计与实现,详细阐述了门控时钟的实现机制,以及为避免引入诱导噪声所采取的措施。经过PowerCompiler分析和VCS仿真,使这种基于门控时钟的低功耗MCU在性能几乎没有损失的情况下,降低了5%～15%的功耗,而芯片面积仅增加4%。最后,采用TSMC0.35umCMOS工艺实现了该低功耗MCU。

Low power has become a new criteria in domain of VLSI design besides speed, complexity and testability. In this paper we investigate the design and implementation of a low power MCU based on clock-gating idle units. We elaborate the principles of applying the clock-gating , describe how to prevent the inductive noise when using it. Simulating it by way of VCS, power analyzing and estimating it by the means of Power Compiler, we find it can be decreased by 5%～15% of total power at the cost of increasing of die size by 4%. Finally, using the TSMC 0.35 static CMOS technology, we implement this low power MCU.