期刊文献+

分簇VLIW DSP调度技术 被引量:1

Scheduling Technology of Clustered VLIW DSP
下载PDF
导出
摘要 分簇VLIWDSP在减少硬件设计复杂性的同时 ,显著地增加了编译器进行指令调度的难度。提出通过在调度中首先进行指令簇划分然后再簇内调度 ,这样在增加很少几条拷贝指令的条件下充分利用分簇的特性提高指令的并行度 。 Clustered VLIW DSP can decrease the complexity of hardware design,but it would increase the difficulty of compiler's instruction scheduling.This paper proposes a way for scheduling that do operation partition at first,and then do list_scheduling in each cluster.This way can improve ILP by adding a few copy operation.
出处 《计算机应用研究》 CSCD 北大核心 2004年第8期80-82,86,共4页 Application Research of Computers
基金 国家"8 6 3"计划重大项目资助 (2 0 0 2AA1Z1110 )
关键词 VUW DSP 编译 指令划分 调度 VLIW DSP Compile OperationPartition Schedule
  • 相关文献

参考文献14

  • 1G Desoli. Instruction Assignment for Clustered VLIW DSP Compilers:A New Approach [ R ]. Technical Report HPL-98 - 13, Hewlett- Packard Company, 1998.
  • 2R Leupers. Instruction Scheduling for Clustered VLIW DSPs [ C ]. Proceedings of the International Conference on Parallel Architecture and Compilation Techniques, Philadelphia, PA,2000.
  • 3Viktor Lapinskii, Margarida F Jacome, et al. Cluster Assignment for High- Performance Embedded VLIW Processors [ J ]. ACM Transactions on Design Automation of Electronic Systems, 2002,7 ( 3 ): 430-454.
  • 4P P Chang, D M Lavery, et al. The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors[ J]. IEEE Transactions on Computers, 1995,44 (3) :353- 370.
  • 5S Rixner, W Daily, B Khailany, et al. Register Organization for Media Processing[ C ]. Proceedings of the 26th International Symposium on High- Performance Computer Architecture.
  • 6S Jang,S Carr,et al. A Code Generation Framework for VLIW Architectures with Partitioned Register Banks[ C]. Proc. of 3rd Int Conf. on Massively Parallel Computing Systems, 1998.
  • 7Viktor Lapinskii, Margarida F Jacome, Gustavo de Veciana. High Quality Operation Binding for Clustered VLIW Datapaths[ C]. Proceedings of IEEE/ACM Design Automation Conference ( DAC' 2001 ) ,2001.
  • 8S-M Moon, K Ebcioglu. An Efficient Resource-Constrained Global Scheduling Technique for Superscalar and VLIW Processors[ C ]. 25th Annual International Symposium on Microarchitecture, Portland, Oregon, 1992.
  • 9J A Fisher. Trace Scheduling:A Technique for Global Microcode Compaction [ J ]. IEEE Transactions on Computers, 1981, C-30:478 - 490.
  • 10E ''Ozer,S Banerjia,T M Conte. Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures [C]. Proceedings of the 31st Annual International Symposium on Microarchitecture, 1998.

同被引文献7

  • 1胡定磊,陈书明,刘春林.分簇结构超长指令字DSP编译器的设计与实现[J].小型微型计算机系统,2006,27(2):348-353. 被引量:7
  • 2张丹红,游珍珍.DSP的多领域应用研究[J].计算机技术与发展,2006,16(3):206-207. 被引量:10
  • 3S.AMahlke,D.C.Lin,W.Y.Chen,R.E.Hank,and R.A.Bringmann,"Effective compiler support for predicated execution using the hpyerblock" in Proceedings of the 25th International Symposl- um on Microarchitecture, pp.45-54, December 1992
  • 4Car,Crest. A Compiler and Simulator for Resear-ch on Embedded and EPIC architecturs. Apr 2007
  • 5S.Adity,V.KathaiI.Elcor's Machine Description System:Version 3.0.July 1998
  • 6V.Kathail,B.Rau.HPL-PD architecture specific- ation.Feb,2000
  • 7ReaCT-ILP Group, Trimaran tutorial. December 1997

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部