门级故障到寄存器传输级故障的映射

Mappings of Gate Level Faults to Register Transfer Level Faults

以一组 74系列集成电路产品和ISCAS85基准电路为例 ,研究了基本寄存器传输级 (RTL)元件的门级单故障到RTL故障的映射关系 .结果表明 :①对大多数电路来说 ,仅考虑电路的单个原始输出端出错将无法达到所希望的门级故障覆盖率 ;②RTL电路的实现不宜包含异或门、与或非门 (AOI)和或与非门 (OAI) ;③在选择差错模型时 ,不同功能的RTL电路需要同时考虑的差错数是不相同的 ,功能相同但仅局部逻辑结构有差别的RTL电路可以考虑相同数目的差错 .这些结论为研究超大规模集成电路的测试、容错设计与验证 ,以及基于故障注入的系统性能评估等技术提供重要依据 .

Fault models are very important for circuit fault testing,fault tolerance design and verification,performance assessment based fault injection.This paper presents an experiment on the study of the mapping relationship between register transfer level (RTL) faults and gate level faults. In this experiment,a group of commercial 74 family integrated circuits and ISCAS85 benchmark circuits are used as RTL primitive components.The experimental results show that it cannot obtain the expected gate level fault coverage if only single erroneous primary output is considered for most circuits,it is not suitable for RTL circuits to implement by XOR gate,AOI gate or OAI gate and different functional RTL circuits must consider different number of primary output errors,and the RTL circuits with same function but different local logical implementations can consider the same number of primary output errors.