摘要
介绍了基于IEEE 114 9.4混合信号测试总线标准的验证电路设计 ,利用复杂可编程逻辑器件 (CPLD)、模拟开关ADG2 0 2A和电压比较器LM311等器件 ,实现了该标准所定义的测试结构。它的设计与可观性实验及可控性实验验证了标准的有效性 ,对于今后推广标准在混合信号芯片中的应用将起到积极的作用。
A method of designing a verification circuit based on IEEE standard for a mixed-signal test bus is introduced. By using a CPLD, analog switches ADG202A and voltage comparators LM311, the boundary-scan test architecture compliant to the standard is implemented. Its design and implementation verified the standard’s effectiveness, and will play an important role in promoting its application in mixed-signal chips in the future.
出处
《电子工程师》
2004年第9期10-13,共4页
Electronic Engineer
