可编程器件设计中跨时钟域的同步设计问题

The Timing Problem of Synchronous Design in FPGA/CPLD

介绍可编程器件异步设计中的亚稳态现象及其可能造成的危害,阐述同步设计的重要性.通过具体的设计实例论证了跨时钟域同步处理的必要性,并给出一种实现跨时钟域同步处理的方法和具体电路实例.

This paper discusses the timing problem in FPGA/CPLD design. It digs out the reasons of this kind of problem and the influence of them on design. Finally, it concludes with some resolutions for the timing design.