Verilog HDL与SystemC的语法等效性

Syntax Equivalence of Verilog HDL and SystemC

针对电子系统设计中使用不同语言制约设计效率的问题,研究了SystemC2.0与VerilogHDL的语法在基本语法结构、时间模型、等待和事件模型、调度模型等方面的等效性,得出如下结论:对于门级以上级别的描述,所有的VerilogHDL的描述总可以在SystemC中找到对应描述;开发EDA设计工具,实现从VerilogHDL描述的知识产权自动转换到SystemC描述是可行的.

The syntax equivalence of Verilog HDL and SystemC2.0 is discussed in detail regard to basic syntax structure, timing model, wait and event module and scheduler module. It is concluded that for gate or upper abstract level of Verilog HDL description, there always exists corresponding SystemC description,and it is feasible to develop an EDA design tool to automatically convert Verilog-based IP to SystemC-based IP.