用Verilog HDL进行FPGA设计的一些基本方法

The Basic Methods of FPGA design using Verilog HDL

随着FPGA技术和自动设计工具的进步,数字电子系统设计的方法正在发生变化。越来越多的工程师开始使用硬件描述语言和高级综合工具进行设计。VerilogHDL作为一种流行的硬件描述语言,在数字系统设计特别是FPGA设计中有着广泛的应用。本文主要介绍了用VerilogHDL进行FPGA设计和优化的一些实用方法,最后还介绍了IP核复用技术在FPGA设计中的应用。

Advances in FPGA technology and design automation tools have been changing the design ways of digital electronic systems. More and More engineers gradually begin to design by using hardware description languages (HDLs) and sophisticated synthesis tools. As a popular hardware description language, Verilog HDL has been widely used in digital system design especially in FPGA design. This paper mainly propose some useful ways of FPGA design and opti mization by Verilog HDL. The IP core reuse technology used in FPGA design is also introduced in the end of this paper.