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RTL数据通路模拟矢量自动生成方法研究与实现 被引量：2

Automatic Simulation Vector Generation for RTL Datapath
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摘要 针对已有的RTL数据通路模拟矢量自动生成方法的不足 ,提出一种利用约束逻辑编辑 (CLP)自动生成数据通路模拟矢量的新方法 该方法首先对给定的VerilogRTL描述采用程序切片进行设计化简 ,然后对化简后的结果基于位向量算术原理生成CLP约束 ,并利用CLP求解器GProlog进行约束求解 ,最终生成满足输出要求的模拟矢量 该方法约束求解速度快 ,生成的约束是统一的 ,得到的模拟矢量较完备 ,能满足模拟验证的要求 实验结果表明 。 A novel constraint logic programming(CLP) based method of automatic simulation vector generation for RTL datapath is presented to reduce the design complexity by program slicing and generate CLP constraints based on bitvector arithmetic for the reduced design. It utilizes GProlog to solve the CLP constraints for producing simulation vectors. The method can generate uniform constraints with quick solution and generating complete vectors to satisfy the needs of simulation. Experimental results show that this approach is efficient and automated in generating simulation vectors for RTL datapath.
作者 李暾 郭阳 李思昆
机构地区 国防科学技术大学计算机科学与技术学院
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2004年第8期1062-1069,共8页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金 ( 90 2 0 70 19 60 3 0 3 0 11) 国家"八六三"高技术研究发展计划 ( 2 0 0 2AA1Z14 80 )资助
关键词 RTL 数据通路 模拟矢量自动生成方法 约束逻辑编辑 CLP VLSI 形式化描述 模型检验 位向量算术 约束求解 VLSI datapath constraint logic programming automatic simulation vectors generation
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献15

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二级参考文献7

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同被引文献30

  • 1鲁巍,吕涛,杨修涛,李晓维.RTL可观测性语句覆盖评估方法[J].计算机辅助设计与图形学学报,2006,18(1):62-68. 被引量：3
  • 2Bushnell M L,Agrawal V D.Essentials of electronic testing for digital,memory and mixed-signal VLSI circuits[M].Boston:Kluwer Academic Publishers,2000
  • 3Jiang T Y,Liu C N J,Jou J Y.Observability analysis on HDL descriptions for effective functional validation[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2007,26(8):1509-1521
  • 4Fallah F,Devadas S,Keutzer K.OCCOM-efficient computation of observability-based code coverage metrics for functional verification[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2001,20(8):1003-1015
  • 5Lv T,Liu L Y,Zhao Y,et al.An observability branch coverage metric based on dynamic factored use-define chains[C]//Proceedings of the 15th Asian Test Symposium,Fukuoka,2006:89-94
  • 6Lv T,Fan J P,Li X W,et al.Observability statement coverage based on dynamic factored use-define chains for functional verification[J].Journal of Electronic Testing-Theory and Applications,2006,22(3):273-285
  • 7Lee J,Patel J H.Architectural level test generation for microprocessors[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1994,13(10):1288-1300
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  • 10Pauli C,Nivet M L,Santucci J F.Use of constraint solving in order to generate test vectors for behavioral validation[C]//Proceedings of High-Level Design Validation and Test Workshop,Berkeley,2000:15-20

引证文献2

二级引证文献7

计算机辅助设计与图形学学报
2004年 第8期

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