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32位浮点嵌入式MCU设计研究 被引量:4

Design of a 32-Bit Floating Point Embedded MCU
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摘要 本文介绍了一个基于RISC体系结构的32位浮点嵌入式MCU的设计实现。该MCU内含128kbit的SRAM、采用哈佛结构、四级指令流水线、32位指令字长和内部43位数据字长。MCU内部设置多个快速寄存器及采用硬连线逻辑代替微程序控制的方法,加快了微处理器的速度,提高了指令执行效率。设计中还采用对寄存器同步写、异步读的方式避免了数据相关问题。 A top-down design of a 32-bit floating point embedded MCU based on RISC structure is presented. This MCU includes 128k bits SRAM, has the Havard structure, 4-stage pipeline, 32-bit instruction and 43-bit internal data. The speed and instruction efficiency of the MCU have been greatly improved by setting multiple high-speed working registers, replacing micro-program with hard-wired logic. The problem of data impact is solved by synchronously writing and asynchronously reading of the registers.
出处 《微电子学与计算机》 CSCD 北大核心 2004年第7期30-33,共4页 Microelectronics & Computer
基金 总装备部科研项目(010STJ003)
关键词 微控制器 浮点 RISC SRAM Micro-controller, Floating point, RISC, SRAM
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参考文献5

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同被引文献14

  • 1徐晨,袁红林,李智.基于C*Core的SoC设计与验证[J].微电子学与计算机,2004,21(7):124-126. 被引量:5
  • 2康书峰,徐美华,冉峰.基于ATmega8515的USB-CAN适配器的实现[J].上海大学学报(自然科学版),2005,11(2):127-132. 被引量:1
  • 3周宁宁,陈燕例,李爱群.基于FPGA技术的浮点运算器的设计与实现[J].计算机工程与设计,2005,26(6):1578-1581. 被引量:11
  • 4黄小平,樊晓桠,贾琳,白永强.“龙腾~RR2”微处理器流水线的设计及优化[J].微电子学与计算机,2006,23(2):144-147. 被引量:9
  • 5FINC M,ZEMVA A.Profiling soft-core processor application for hardware/software partitioning[J].Journal of System Architecture,2005,51:315-329.
  • 6ROMAN L,FANK V.A Study of the speedups and competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitoning[EB/OL].[2005-06-03].http://www.cess.uci.edu/conference-procedings/data-2005/vahidfpga.pdf.
  • 7SOTIRIOS G,ZIAVRAS.Processor design based on dataflow concurrency[J].Microprocessors and Microsystem,2003,27:199-220.
  • 8Stallings W.计算机组织与体系结构:性能设计[M].张昆藏,译.北京:清华大学出版社,2006:397-400
  • 9夏宇闻.Verilog数字系统设计[M].北京:北京航空航天大学出版社,2004:50-74
  • 10http://www.opencores.org/cvsget.cgi/AVR_Core[EB/OL]

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