系统芯片总线分析模块的设计

Design of Bus Analyzer for System on chip

提出了增加系统芯片观测性的一种新颖实现方法,即增加一个总线分析模块以实现对芯片的系统级监控。该总线分析模块由采样、存储、调试以及上位机接口单元组成。用户通过上位机软件可以方便地设置指令的采样点,选择自己需要的总线采样信号,对采样结果进行查询等。总线分析模块通过存储单元实现了对多次采样结果的存储。

In this paper we present a new method to enhance the observability of System on Chip. We succeed this by adding a new analyzing module on system bus. Our bus analyzing module is comprised of a Sampling Unit, a Memory Unit, a Debug ging Unit and a Host Interface Unit. With the help of our host software user can conveniently set sampling points, select sampling signals and query sampling re sults. The memory unit can save many sampling results.