IDCT IP核的VLSI结构

Architecture of VLSI for IDCT IP Core

介绍了一种新型的IDCTIP核的VLSI结构,这种并行结构结合分布式算法和基于存储器的查找表,系统自顶向下分解为模块,设计出一个不需要乘法器的高性能IP核,可以实时处理MPEG2MP@ML。

This paper introduces a new VLSI architecture for IDCT IP core. The pa rallel architecture combines distributed algorithm and look-up table based memor y. The system is divided into modules from the top to down.. A high performance IP core is designed without multiplier and can process MPEG2 MP@ML in real time .