基于FPGA实现Viterbi译码器IP-Core的技术研究

Realizing the technology of implementingViterbi Decoder IP-Core Based on FPGA

提出一种基于FPGA实现Viterbi译码器的结构,利用该结构实现的Viterbi译码器具有通用性。在设计中充分利用FPGA的特点,使Viterbi译码器的译码速度得到提高,并且译码延时比较小。

In this paper a Viterbi decoder structure based on FPGA is presented. The decoder that is implemented in this structure have general-utility. In the design the auther considers the FPGA's characteristics to improve the decoder's rate and shorten the delay.