摘要
描述了超前进位加法器的一种优化设计。在结构上采用按4位分组进行超前进位的方法达到并行、高速的目的。为了在高速运算的同时降低功耗,对求和式子进行了逻辑变换;在晶体管级进行优化的单元电路设计,可减小延时、降低整个电路的面积和功耗。
An optimized design of CLA is described in the paper. The look-ahead carry is computed by 4-bit’s groups. Logic transformation is performed in order to achieve low-power operation. Optimized cells are designed on the transistor-level to increase the speed and reduce the area of the CLA circuit.
出处
《半导体技术》
CAS
CSCD
北大核心
2004年第8期65-68,共4页
Semiconductor Technology
关键词
超前进位加法器
优化设计
逻辑变换
晶体管
CLA
optimized design
branch-based logic
design based on transistor
