摘要
论文提出了一个超大规模集成电路(VLSI)片上三维互连线寄生电容精确提取流程模型。文中研究了该提取流程中计算区域的自动划分问题,并对该流程各个模块进行了设计。
In this paper,an on-chip parasitic capacitanc e extraction model of VLSI interconnections has been presented which captures3D geometry from layout design and process technology information.An automatic pl anning of computa-tional region is discussed in detail and program modules of t he extraction flow have been designed.
出处
《计算机工程与应用》
CSCD
北大核心
2004年第26期106-108,共3页
Computer Engineering and Applications
基金
国家自然科学基金重大研究计划重点项目:互连线建模
仿真和综合(编号:90307017)
关键词
VLSI
互连线
电容提取
VLSI ,interconnections,capa citance extraction
