组合逻辑电路中多余项的设计应用

Design application of reduindant item of combinational logical circuit

在小规模集成器件设计组合逻辑电路时,采用最简单与一或表达式不一定是最佳电路结构。本文给出了采用或非器件进行多余项合并求对偶方法得出最佳逻辑电路的设计过程。

When we design combinational logical circuit by using small scale integrated divice, the simplest AND - OR expression may not be the best circuit construction. In this paper, it gives a kind of design process of best logic circuit by merge redundant item and dualization method using.