级联型PLL时钟处理器对系统定时影响最小

Real Data Cuts Timing Mumbo-jumbo for Cascaded PLL Designs

本文对一个采用5个串联PLL的特殊而又典型的实验所获得的性能加以研究,并采用该方案把设计师所关心的种种不良影响着力体现出来。

In this article we are going to look at the performance produced by of a specific, but typical experiment using five PLLs connected in series. Whiledesigning five PLL devices in a series configuration is not advised, it is specifically being used here to accentuate and amplify the effects that weare interested in.