用深度优先搜索流处理的比特平面并行SPIHT编码结构

Bit plane-parallel VLSI architecture for a modified SPIHTalgorithm using depth-first search bit stream processing

提出了采用并行的SPIHT编码结构,每一个比特平面的编码信息可以同时获得,空间定位生成树重要性标志位图的继承关系则通过逻辑运算得到,并且详细说明了VLSI结构.与现有的结构相比,该结构具有并行度高,没有中间缓冲,以单个生成树进行独立扫描编码,具有一定的抗误码扩散能力,处理速度有明显提高,图像质量可满足大多数应用要求.

We present a bit plane-parallel architecture for a modified SPIHT algorithm using depth-first search bit stream processing which is suitable for VLSI implementation. In the architecture, the coding information of each bit plane can be obtained simultaneously. That is, the ancestor-descendant relationship between coefficients of the tree structure can be calculated by logical operators. Then, the corresponding VLSI architecture for implementing the formulated requirements is presented. Compared with other architectures, this has advantages of high parallelism, no intermediate buffer and the ability to scan with error resilience as a single tree. The experimental results show that the proposed architecture reduces the processing time greatly compared with others. The quality of images can satisfy most application fields.