期刊文献+

基于IP的系统芯片(SOC)设计 被引量:2

Design of SOC based on IP core
下载PDF
导出
摘要 随着集成电路设计与工艺技术水平的提高,出现了系统芯片(SOC)的概念。本文介绍了基于IP的SOC设计方式的设计流程,指出了其与传统IC设计方法的不同。讨论了支持SOC设计的几种关键技术,并对SOC的技术优势及发展趋势作了全面阐述。 With the improvement of IC design and technological level, a new conception of SOC is established. The paper describes the design process of SOC based on IP and indicates the differences from traditional IC design. As well as some key technologies supporting SOC, the advantages and developing trend of it are also discussed in the paper.
出处 《信息技术》 2004年第10期62-64,69,共4页 Information Technology
关键词 IP核 系统芯片(SOC) 设计方法 IP core system on-chip design method
  • 相关文献

参考文献5

二级参考文献8

  • 1[1]Martin G. Design methodologies for system level IP[C]. In:Design, Automation and Test in Europe, 1998,Proceedings, 1998 Page(s):286~289
  • 2[2]Lahiri K, Raghunathan A, Dey S. Fast performance analysis of bus-based system-on-chip communication architectures[C]. In:Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on, 1999 Page(s):566~572
  • 3[3]Benini L, Macchiarulo L, Macii E, Macii E, Poncino M. From architecture to layout:partitioned memory synthesis for embedded systems-on-chip[C]. In:Design Automation Conference, 2001. Proceedings, 2001 Page(s):784~789
  • 4[4]Sassatelli G, Cambon G, Galy J, Torres L. dynamically reconfigurable architecture for embedded systems. In:Rapid System Prototyping[C], 12th International Workshop on, 2001., 2001, Page(s):32~37
  • 5[5]Yang L. T, Muzio J.Built-in self-testable data path synthesis[C]. In:VLSI, 2001 Proceedings. IEEE Computer Society Workshop on , 2001, Page(s):78~84
  • 6[6]Santos M B, Goncalves F M, Teixeiral I C Teixeira J P. RTL-based functional test generation for high defects coverage in digital SOCs[C]. In:European Test Workshop, 2000. Proceedings. IEEE, 2000, Page(s):99~104
  • 7[7]Jaewon Oh, Padram M. Gated clock routing for low-power microprocessor design[C]. In:Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume:20 Issue:6, June 2001, Page(s):715~722
  • 8[8]Chauhan P, Clarke E.M, Lu Y, Wang D.Verifying IP-core based system-on-chip designs[C]. In:ASIC/SOC conference, 1999. Proceedings. Twelfth Annual IEEE International, 1999, Page(s):27~31

共引文献20

同被引文献9

引证文献2

二级引证文献8

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部