利用微电子测试图形研究CMOS IC的锁定效应

Study on the Latch-up Effect of CMOS IC by Using Microelectronic Test Patterns

体硅CMOS IC内不可避免地存在着寄生pnpn四层结构,在一定条件下,导致器件闭锁失效.本文结合专门用于研究CMOSIC内锁定的微电子测试图形,对以设计、工艺制备的一系列组合测试结构,进行测试,并对锁定现象作对比分析,提出了优化设计的途径.

The parasitic pnpn structure exists inherently in bulk CMOS IC.It leads devices to Latch-up failures under certain conditions.This paper studies Latch-up behavior comparatively through a series of tests on a set of composite-test Structures which have been designed and technologically manufactured.Then the approaches to optimum design are proposed.