高速通用DES加解密芯片设计与实现

Design and implementation of hign-speed and general-interface DES secuity chip

现代网络与通信技术高速发展,对信息安全提出了更高的要求,实现高速可靠的数据加密越来越重要.通过对DES加密技术的研究,优化DES加解密算法,运用流水线技术,采用并行处理,在单片廉价FPGA(XC2S50)上设计实现了高速通用的DES加解密芯片.

With the development of the modern network and communication,it's more necessary to encrypt the high-speed information.In this paper,by optimizing the DES arithmetic,using pipe line, adopting parallel technology,the single chip of high-speed and general-interface DES Secuity based on FPGA(XC2S50) is implemented.