基于FPGA的Kohonen竞争网络硬件实现

Research on Kohonen Competitive Network Hardware Realization by FPGA

本文介绍了神经网络VLSI硬件实现的基本情况和VerilgHDL硬件设计方法的概念,在此基础上利用FPGA设计出了Kohonen竞争网络硬件电路,其工作频率为33Mhz,并对其工作过程进行了较详细的分析,给出了综合仿真的测试结果。

This paper introduces the basic complexion of neural network VLSI hardware realization and the concept of VerilgHDL hardware's design. Based on that, it designs Kohonen competitive network hardware circuit by utilizing FPGA, which working frequency is 33Mhz. Then in this paper detailedly analyses its working process, and provides the testing result of integrated simulation.