卫星信息处理系统中基于FPGA的时序电路设计

A Design of Sequential Circuit base on FPGA in the Signal Processing System of Satellite

本文卫星信息处理系统中基于FPGA的时序电路设计进行了研究 ,给出了系统构成 ,进行了软件设计和硬件设计及系统实现工作 ,并认真分析了各种时序之间的关系 ,提出了利用复杂可编程逻辑器 (CPLD)方法来提高单片机系统的集成化、智能化和可靠性 ,有效的压缩了占有空间 ,利用PC机实现了测试设备之间的信息连接。实验结果表明 :该系统研制是成功的 。

A design of sequential circuit base on FPGA in the signal processing system of satellite is realized in this paper, which gives the structure of the system, software and hardware are designed. The relations of sequence are analyzed. Occupation space is effectively compressed. The method (CPLD) has been proposed to improve the integration、intelligent and reliability of the single-chip microcomputer system, PC is used to transfer information among multi equipments. Practice results prove this design is successful and is used in the engineering.