基于FPGA的3.125Gbits串行通道设计实验

An Experimental Design of 3.125 Gbps Serial Channel Based on FPGA

本设计实验是为了验证如何用现场可编程门阵列 (FPGA)实现 3.12 5Gbit s的串行通道设计。设计中使用了Xilinx公司的Aurora链路层协议 ,以及Virtex ⅡPro器件中内置的 3.12 5Gbit s高速串行收发器。文中描述该设计所涉及的主要实现方法 ,包括Aurora协议接口设计、特殊的片上时钟电路设计、片上存储器设计以及芯片引脚和布局设计等。

This experimental design is performed to validate a 3.125 Gbps serial port running in FPGA. The design uses a Xilinx Virtex-Ⅱ Pro FPGA and is based on the Aurora link layer protocol provided by Xilinx and uses the 3.125 Gbps multi-gigabit transceiver embedded in the Virtex-Ⅱ Pro FPGA. This paper describes some considerations in the design including the interface design for FPGA based Aurora protocol, special on-chip clocking circuit design, on-chip memory, pin-out and layout design.