期刊文献+

精确时延模型下满足时延约束的缓冲器数目最小化的算法(英文)

Timing Optimization by Inserting Minimum Buffers with Accurate Delay Models
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摘要 提出了在精确时延模型下 ,满足时延约束的缓冲器数目最小化的算法 .给出一个两端线网 ,该算法可以求出满足时延约束的最小缓冲器数目 .运用高阶时延模型计算互连线的时延 ,运用基于查找表的非线性时延模型计算缓冲器的时延 .实验结果证明此算法有效地优化了缓冲器插入数目和线网的时延 ,在二者之间取得了较好的折中 . An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第11期1409-1415,共7页 半导体学报(英文版)
基金 国家自然科学基金 (批准号 :60 1760 16) 国家高技术研究与发展计划 (批准号 :2 0 0 2 AAIZ14 60 )资助项目~~
关键词 缓冲器插入 互连优化 布图 VLSI buffer insertion interconnect optimization layout VLSI
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参考文献9

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