能量回收阈值逻辑电路

Energy Recovery Threshold Logic

通过把阈值逻辑应用在能量回收电路中 ,提出了一种新的电路形式——能量回收阈值逻辑电路 (energy re-covery threshold logic,ERTL) .阈值逻辑的应用 ,使 ERTL 电路的门复杂度大大降低 ,同时进一步降低了功耗 .分别以 ERTL 电路和静态 CMOS电路设计了 4位超前进位加法器 ,两个加法器采用相同的结构 .ERTL 加法器逻辑电路的晶体管数目只占静态 CMOS加法器的 6 3% ,与现有的能量回收电路相比 ,硬件开销减少 .设计使用的是TSMC0 .35 μm工艺 ,分别在 3V和 5 V工作电压下对电路进行 Spice仿真 .仿真结果显示 ,在实际的工作负载和工作频率范围内 ,ERTL 电路的能耗只有静态 CMOS电路的 14 %～ 5 8%

A new energy recovery logic style (energy recovery threshold logic,ERTL) based on threshold logic is presented.With threshold logic,ERTL has very low power dissipation and low gate complexity.4-bit ERTL carry lookahead adder(CLA) and static CMOS CLA are designed respectively with the same architecture.The transistor counts of ERTL CLA logic circuits is only 63% of static CMOS CLA.Compared to previous energy recovery logic designs,ERTL has low hardware cost.The adders are designed using 0.35μm TSMC CMOS technology.The circuit is simulated at 3V and 5V.Based on the results of Hspice simulation,for a practical load and a practical range of frequencies,ERTL dissipates only 14%～58% of the energy of the static CMOS.