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使用SDF图描述的嵌入式DSP系统存储优化

Memory Optimization for Embedded DSP Systems Represented as Synchronous Dataflow Graphs
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摘要 提出一种嵌入式DSP系统的存储优化方法 该方法利用遗传算法求得存储需求量较少的同步数据流 (Syn chronousDataFlow ,SDF)图顶点调度序列 ;使用TPFIFO(Two PortFIFO)数据缓冲模型来实现顶点输入边和输出边的存储共享 ,以进一步提高数据缓冲的利用率 An approach for reducing memory requirementf of embedded DSP systems is presented Such an approach is based on a genetic algorithm to efficiently explore the exponential search space of actor firing orders A two-port FIFO buffer model is applied to improve the buffer utilization by allowing two simultaneous accesses to the same buffer Experimental results prove the significance of the proposed approach
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2004年第11期1575-1579,共5页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金 ( 69873 0 10 )资助
关键词 嵌入式系统 同步数据流图 存储优化 遗传算法 embedded system synchronous dataflow graphs memory optimization genetic algorithm
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参考文献7

  • 1Murthy P K, Bhattacharyya S S. Shared buffer implementations of signal processing systems using lifetime analysis techniques [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(2): 177~198
  • 2Oh Hyunok, Ha Soonhoi. Data memory minimization by sharing large size buffers [A]. In: Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, 2000. 491~496
  • 3Bhattacharyya S S, Murthy P K, Lee E A. APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations [J]. Journal of Design Automation for Embedded Systems, 1997, 2(1): 33~60
  • 4Zitzler E, Teich J, Bhattacharyya S S.Evolutionary algorithms for the synthesis of embedded software [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(4): 452~455
  • 5Oh Hyunok, Ha Soonhoi. Fractional rate dataflow model for efficient code synthesis [J]. The Journal of VLSL Signal Processing, 2004, 37(1): 41~51
  • 6Rha Kyoungseok, Choi Kiyoung. Area-efficient buffer binding based on a novel two-port FIFO structure [A]. In: Proceedings of the 9th International Symposium on Hardware/Software Co-design, Copenhagen, 2001. 25~27
  • 7Murthy P K, Bhattacharyya S S. A buffer merging technique for reducing memory requirements of synchronous dataflow specifications [A]. In: Proceedings of the 12th International Symposium on System Synthesis, San Jose, 1999. 78~84

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