RTL验证框架——HRV

RT-Level Verification Framework—HRV

设计并实现了一个RTL覆盖率驱动的验证框架HRV ,它集成了自主开发的基于程序切片技术的设计抽取器、基于VCD文件的代码覆盖率分析器以及基于路径和基于断言的模拟矢量自动生成方法 实验结果表明 ,HRV通过集成多种验证工具 ,提高了模拟验证效率 。

This paper presents design and its implements for a coverage-driven verification framework—HRV for VLSI RTL designs HRV integrated program slicing based design extractor, VCD file based coverage analyzer, path-based and assertion-based automatic simulation vectors generator Experimental results show that HRV improve the efficiency of simulation verification, accelerate the errors detecting and locating for RTL HDL descriptions