摘要
研究了HUFFMAN解码器在集成电路上的实现问题,以MPEG-2AAC(先进音频编码)HUFFMA为研究对象,在研究解码码表的特点以及简化解码算法的基础上设计出高速HUFFMAN解码电路。此解码电路已经在ALTERA的FPGA上通过测试,系统能稳定运行在100MHz,输出数据平均达到约1.0Gbits/sec的带宽。
This paper presents a circuit of high-speed HUFFMAN decoding operation by studying the characteristic of the decoding tables and simplifying algorithm of decoding . It takes much smaller memory in size and the decoding becomes significant faster. The design has been implemented on FPGA (Altera EP1S10F780C6 ) and it can run stably at the speed of 100 MHz with high output bandwidth (about 1.0Gbits/sec average).
出处
《微电子学与计算机》
CSCD
北大核心
2004年第10期182-185,共4页
Microelectronics & Computer
