摘要
设计了一种基于锁相环宽输出范围(10 ~ 160M)的频率综合器,着重介绍了其中的压控振荡器(VCO)部分,采用单端、电流控制型的环振,使之在整个输出范围内,即0 ~ 120 ℃、工艺的ss ~ ffcorner,增益(Kvco)的变化在3倍以内。无需根据输出频率对电荷泵的充、放电电流或环路滤波器中的电阻作不同设置,环路的衰减因子就可控制在可接受的范围内,并降低了对其它环路参数的要求。设计基于标准0.6μm N-WELL CMOS 工艺,5V供电。
Phase-lock loop(PLL)-based frequency synthesizer which has wide operating fre-quency is described. The VCO utilizing a ring of single-ended current-steering amplifiers(CSA) pro-vides a relative stable loop gain(Kvco vary less than 3 times) in whole frequency range(10~160M) from0~120℃, ss^ff corner of process. This makes it practicable to control the damping factor in anacceptable range without configuring the charge pump or loop filter resistor according to the outputfrequency. Design bases on a standard 0.6-μm N-WELL CMOS process, 5V supply.
出处
《半导体技术》
CAS
CSCD
北大核心
2004年第12期48-51,共4页
Semiconductor Technology