期刊文献+

应用边界扫描技术提高电路板可测试性的两种优化问题 被引量:2

Two Kinds of Optimization Problems of Applying Boundary Scan Technology to Improve the Testability of Circuit Board
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摘要 边界扫描测试技术很好地解决了VLSI电路诊断、测试的困难问题,得到了广泛的应用。作者在查阅大量文献资料的基础上,总结出了边界扫描技术在提高电路板可测试性上的两种优化问题:即设计过程中设计复杂性和测试性改善的优化,以及在测试生成算法中紧凑性与完备性优化的问题,论文详细分析了这两种问题,分析比较了相关的优化算法,并对这两种优化问题未来的发展方向进行了预测。 Boundary-Scan test technology well resolved the problem of VLSI circuitry diagnosis and test and has gained broad applications. Two kinds of optimization problems of applying Boundary-Scan technology to improve the testability of circuit board are summarized based on reading abundant literature , namely, the optimization problem between design complexity and testability improvement in the process of design and the optimization problem between compact test vector and diagnosis capacity of test generation algorithm. These two optimization problems are analyzed in detail and pertinent optimization algorithms are compared. At last, the development trends of these two kinds of optimization problems are forecasted.
机构地区 装甲兵工程学院
出处 《微电子学与计算机》 CSCD 北大核心 2004年第11期43-46,共4页 Microelectronics & Computer
关键词 可测试性设计 边界扫描 优化 算法 DFT, Boundary-scan, Optimization, Algorithm
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参考文献7

  • 1温熙森,等著.智能机内测试理论与应用.北京:国防工业出版社.2002.87-132.
  • 2P Goel and M T McMahon. Electronic Chip in-place Test.Intl Test Conf. 1982. 83~90.
  • 3P T Wagner. Interconnect: Testing With Boundary Scan.Intl Test Conf. 1987. 52~57.
  • 4胡政,黎琼炜,温熙森.边界扫描测试向量生成的抗混迭算法[J].电子测量技术,1998,21(1):8-12. 被引量:14
  • 5A Hassan, J Rajski and V K Agarwal. Testing and Diagnosis of Interconnects using Boundary Scan Architecture.Intl Test Conf. 1988. 126~137.
  • 6Chi W Yau and Najmi Jarwala. A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects. Intl Test Conf. 1989. 71~77.
  • 7胡政,钱彦岭,温熙森.边界扫描测试优化算法——极小权值-极大相异性算法[J].测控技术,2000,19(9):9-11. 被引量:9

二级参考文献8

  • 1IEEE Standard Test Access Port and Boundary-Scan Archirecture,IEEE Std 1149.1-1990.
  • 2M.V. Tegethoff K. P. Parker "IEEE Std 1149. I Where Are We? Where From Here" IEEE D&T of Computers Summer 1995, pp53-59.
  • 3W.k. Kautz,"Testing of Faults in Wiring Interconnects" ,IEEE Transaction on Computer Vol C-23,No. 4,1974,pp.358-363.
  • 4P. Goel and M. T. McMahon," Electronic Chip-in-place Test," Proc. Intl. Test Conf.1982,pp 126-137.
  • 5A. Hassan,J Rajski,and V.K. Agarwal, "Testing and Diagnosis of Interconnects using Boundary Scan Architecture," Proc. Intl. Test Conf. 1988,pp. 126-137.
  • 6Najmi Jarwala and Chi W. Yau "A New Framework for analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects Proc. Intl. Test Conf. 1989,pp. 63-70.
  • 7胡政,杨拥民,温熙森.应用边界扫描机制实现电子设备系统级测试[J].电子测量技术,1997,20(3):26-30. 被引量:5
  • 8胡政,黎琼炜,温熙森.边界扫描测试向量生成的抗混迭算法[J].电子测量技术,1998,21(1):8-12. 被引量:14

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