FSM状态间逻辑条件检验的算法研究

A STUDY OF ALGORITHMS FOR VALIDATING LOGIC CONDITIONS AMONG FSM STATES

有限状态机(FSM)是VLSI控制结构的一种映射,它的自动综合成为设计自动化的一个十分重要的环节和途径。本文讨论在FSM自动综合中输入阶段的状态间逻辑条件检验的问题,研究分析状态间逻辑条件检验的相互关系及影响,并提出了FSM状态间逻辑条件检验的优化算法,从而使时间复杂度降低,实现更加简便。最后,本文给出了优化算法的流程和一些实验结果,结果令人满意。

Finite state machine (FSM) is a reflection of VLSI control path, and its automatic synthesis becomes a very important step of design automation (DA). In this paper, we will discuss the problem of validating logic conditions among FSM states in the input phase of FSM automatic synthesis process, analyse the interaction between validations of logic conditions among FSM states, and propose a optimal algorithm for validating logic conditions among FSM states that will decrease the time complexity and be easy to implement. Finally, the flowchart of our optimal algorithm and some experimental results are also presented in this paper.