一种逻辑仿真测试平台的设计

Design of a Platform for Logic Simulation and Testing

目前在开发网络设备的大规模数字系统中,仿真验证阶段自动化程度不高,以至投入的人力大、产品开发周期长。该文针对这种情况,提出了ATM、IP、SDH领域内的一种逻辑仿真测试平台(以下简称平台)的程序设计方案。平台由仿真器启动,支持激励数据的自动化生成和分析验证的自动化进行,并且平台的通用性设计使得它可以在不同的操作系统下适用于较多的逻辑业务。实践表明,根据该设计方案开发的平台,在各个部门的推广使用,明显提高了部门的生产效率,显著缩短了产品的开发周期,节省了人力。

These days in the process of developing large scale digital system, the phase of logic simulation and testing is poorly automatized which results in more labor input and a bit long product development period. Aiming at the situation, this paper puts forword the design of a platform for logic simulation and testing within the field of ATM,IP and SDH. The platform is called by a simulator,then it can produce stimulating data and validate output data automatically.It is also an all-purpose design so that it can be used for many logic projects under different operating systems. As practice shows,the wide use of the platform in relative departments apparently raises the production efficiency, shortens product development period and saves the labor.