一种8bRISC微处理器的综合

Synthesis of an 8 b RISC MCU

近年来 ,随着微电子技术的飞速发展 ,微处理器以其突出优点广泛应用于各个领域。微处理器 IP核的设计也随之成为业界关注的焦点。综合是进行微处理器 IP核设计的一个重要步骤。本文介绍一种 8b RISC微处理器的综合过程 ,着重论述 ROM,RAM模块的综合方法及与其他模块的接口问题。所使用的软件为 Synopsys的 Design Analyzer以及 Avan-ti!的 Rapidcompiler,综合库是中芯国际 0 .35μm的综合库。综合出的网表已通过门级验证。

Recently, with the rapid development of the microelectronics technology, MCUs are widely used in many fields. The design of MCU IP core also becomes a focus of attention. Synthesis is an important step when we design a MCU IP core. This paper introduces the synthesis process of an 8bit RISC MCU in detail. The synthesis method of ROM,RAM and the problem of how to connect them with other modules are emphasized. Design analyzer,Rapidcompiler and SMIC35 library are used. The gatelevel netlist has been verified.