摘要
系统分析了高速电流型CMOS数模转换器的设计方法。设计了一种采样率为100ms/s,分辨率为8bit,电源电压为3.3v的CMOS电流型DAC。采用同步锁存技术增加了转换速度。电路仿真结果表明在采样率为100Ms/s,输入信号从直流到Nyquist频率,无杂散动态范围(SFDR)为59dB。积分线性误差(INL)和微分线性误差(DNL)分别为±0.5LSB和±0.3LSB。在采样率为100Ms/s,电源电压为3.3v时的功耗小于300mw。电路采用0.35um标准CMOS工艺实现。
System analysis the design methodology of high speed current-steering cmos dac。A 3。3v 8bit 100Ms/scurrent-steering dac is presented。The proposed synchronized latch technique increase the conversion speed of dac。Simulation results show that the spurious-free-dynamic-range is better than 54dB for sampling frequency up to 100MSamples/s and signals from dc to nyquist frequency。Monte-Carlo simulations show that the integral non-linearity(INL) and differentialnon-linearity(DNL) is better than ±0。5LSB and ±0。3LSB respectively。The dac dissipated less than 300mW from 3.3vpower supply at 100ms/s sampling rate。The circuit has been designed in a standard 0.35um cmos process.
出处
《电子质量》
2004年第10期54-55,60,共3页
Electronics Quality