摘要
DRFM是电子对抗措施系统中的核心部件 ,它将雷达信号下变频后的信号进行采样保存 ,再延时转发出去 ,从而实现距离上的欺骗干扰。通过PLD能够得到FIFO 4路精确的时钟和读写使能信号 ,从而提高了整个系统的工作时钟精确度和延时的灵活性。提出一种基于可编程逻辑器件 (PLD)的数字射频存储器(DRFM)的设计新方法 ,并通过仿真部分实现。
The digital radio frequency memory(DRFM) is the core of the electronic countermeasure (ECM),it samples and saves the signal which is from down frequency conversion of radar signal,then postpones and sends it out, thus the deception and interference in distance are realized.Through the programmable logic device(PLD),the first-in first-out(FIFO)'s four precise clock and write enabling signals can be achieved,thus the accuracy of the whole system and flexibility of the time delay are increased.This paper brings forward a new method of DRFM design based on PLD,and realizes it partly through simulation.
出处
《舰船电子对抗》
2004年第5期6-9,共4页
Shipboard Electronic Countermeasure
