摘要
提出了一种保护图像中最重要的边缘信息的量化策略。仿真结果表明,与普通量化方法(如TMN系列代码)相比,新方法以较小的运算量为代价使边缘信息得到有效保护,从而在降低码率的同时更好地保持了图像的质量。
This paper is about an ASIC (Application Specific Integrated Ciruit ) solution for H.264 decoder and its FPGA (Field Programmable Gate Array) verifi cation platform. This solution has faster decoding speed and less power consumpt ion, which greatly solves the problems of low speed and high power consumption d ue to the increased complexity of the algorithm of H.264 decoder. This paper als o introduces the FPGA verification platform in detail since verification is of c ritical importance for the success of a large scale SoC chip.
出处
《电视技术》
北大核心
2004年第10期47-49,共3页
Video Engineering
